Recent requirements for higher functions and reduction in a weight and a size in electronics have accelerated high-density integration and high-density mounting of electronic components, and increasing size reduction of a semiconductor package used in these electronic devices.
Since there is a limit to size reduction in a conventional type semiconductor package using a lead frame, there have been recently proposed a ball grid array (BGA) in which a semiconductor chip is mounted on a circuit board and an area-mount type semiconductor package such as a chip scale package (CSP). In these semiconductor packages, a semiconductor chip mounted in BGA is connected to a circuit board by a known manner such as wire bonding, TAB (Tape Automated Bonding) and flip-chip (FC) bonding, and there have been frequently proposed BGA and CSP structures employing a flip-chip bonding system which is advantageous for size reduction of a semiconductor package.
It is believed that mounting by flip-chip bonding is advantageous in that a mounting area can be reduced in comparison with wire bonding. In addition, flip-chip mounting has a feature of good electric properties because of a short circuit wiring. Flip-chip mounting is particularly suitable for a mobile device circuit strongly required to be size-reduced and thinned and a high-frequency circuit in which electric properties are important.
An interposer (multilayer circuit board) used for connection of a semiconductor chip in flip-chip mounting generally has a core layer, a conductor circuit layer and an insulating layer. For addressing further high-density mounting and speeding-up of an operating frequency in terms of such a multilayer circuit board, there has been proposed a thin build-up interposer which address a high frequency by reducing a thickness of a core layer or employing a coreless structure without a core layer which uses, as an interposer, a laminate consisting of a resin having a wiring pattern to reduce the overall thickness of the interposer and thus to reduce a length of interlayer connection (see, for example, Patent Document No. 1).
In a flip-chip mounted semiconductor package, a gap between a semiconductor chip and a circuit board is generally filled with a resin composition for reinforcement (underfill) for ensuring reliability of a joint in a semiconductor chip, a circuit board and a metal bump. A thermosetting resin such as an epoxy resin has been widely used as an underfill material.
This semiconductor package is produced by placing the active face of a silicon chip facing a circuit board, electrically connecting the face to the circuit board via a conductive material and filling the gap between the silicon chip and the circuit board with a thermosetting resin composition, which is then cured. This thermosetting resin composition contains a linear aliphatic hydrocarbon compound having 10 or more and 30 or less carbon atoms which chemically attaches a thermosetting resin. Thus, a silicon chip can be removed at a low temperature with a small shear force without damage to the silicon chip or the circuit board while higher temperature cycle reliability is ensured (See, for example, Patent Document No. 2).
Patent Document Nos. 3 and 4 have described an interlayer insulating layer used for a multilayer printed wiring board. Patent Document No. 3 has described that copper foils are laminated via one prepreg. Patent Document No. 4 has described that copper foils are placed on both sides of piled prepregs and the laminated. In other words, interlayer insulating layers sandwiched by interconnections are resin layers made of an identical material.
Patent Document No. 1: Japanese published application No. 2006-24842.
Patent Document No. 2: Japanese published application No. 1999-233571.
Patent Document No. 3: Japanese published application No. 2007-59838.
Patent Document No. 4: Japanese published application No. 2008-37881.